HANDS-ON TECHNICAL TRAINING IN PHYSICAL DESIGN USING CADENCE EDA TOOL, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

Physical design is the process of turning a design into manufacturable geometries. It comprises a number of steps, including floor planning, placement, clock tree synthesis, and routing. Physical design begins with a netlist, which is synthesized from RTL. The netlist describes the components of a circuit and how they connect.
Floor planning is the first major step. It involves identifying which structures should be placed near others, taking into account area restrictions, speed, and the various constraints required by components. Partitioning divides a chip into functional blocks.
Placement determines the locations of each component or block on the die, considering timing and interconnect length.
Clock tree synthesis involves inserting buffers or inverters such that the clock is distributed evenly to sequential elements in a design, minimizing skew and latency.
Routing determines the paths of interconnects, including standard cell and macro pins. This stage completes all connections defined in the netlist, ideally in the most efficient way and without violating timing constraints.
The final output of the physical design process is typically GDSII, a data format representing layout information.