Three-day hands-on training on “System Design using FPGA”, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

The department of Electronics and Communication Engineering, in association with the student's association SPARTRANZ, organizes a three-day hands-on training on “System Design using FPGA” between 07.11.2024 and 09.11.2024 at the VLSI laboratory. Ms.R. Shayamal Devi will handle the session. On day 1, 07.11.2024, we discussed the following topics under Digital Electronics and VLSI domain.

·        Digital Electronics: Combinational and Sequential Logic

·        Importance of logic gates in digital circuit design

·        Finite state machine

·        Introduction to VLSI

·        CMOS VLSI Design 

The students' performance was assessed with a quiz at the end of the first day of the session. The resource person discussed the design flow of ASICs (Application Specifications Integrated Circuits) and their function in VLSI design on day two, 08.11.2024. After talking about the differences in features between ASIC and FPGA, they demonstrated a practical Verilog training session using basic programs such as adders, subtractors, multiplexers, and demultiplexers. The resource person delivers a brief overview of the Verilog system on day three, 09.11.2-2024, and exhibits the basic program adders, subtractors, and finite state machines. The fundamental distinctions between VHDL, Verilog HDL, and System Verilog were covered in the last session. The students asked questions and engaged in lively discussion with the resource person and clarified their doubts.

 At the end of the session, students were able to:

 1. Understand combinational, sequential logic circuits, and finite state machines.

 2. Role of ASIC and FPGA in VLSI Engineering

 3. Write verilogHDL code for combinational and sequential logic circuits.

 4. Write system Verilog code for simple combinational circuits.

 5. Aware about different roles of VLSI engineers in industry