Workshop on Physical Design Automation with Cadence for VLSI Engineers, KPR Institute Engineering and Technology, Autonomous Engineering Institution, Coimbatore, India

Title
Workshop on Physical Design Automation with Cadence for VLSI Engineers

Hybrid Event
Workshop on Physical Design Automation with Cadence for VLSI Engineers
Workshop Dept. Level
DATE
Oct 10, 2025 to Oct 11, 2025
TIME
09:00 AM to 04:00 PM
DEPARTMENT
EC
TOTAL PARTICIPATES
44
Workshop on Physical Design Automation with Cadence for VLSI Engineers Workshop on Physical Design Automation with Cadence for VLSI Engineers
Summary

The Workshop on Physical Design Automation using Cadence tools for VLSI Engineers provided participants with hands-on training in industry-standard EDA tools like Cadence Virtuoso, Innovus and genus covering the full physical design flow from schematic capture to layout, placement, routing, and verification. The attendees gained valuable skills in analog and digital circuit layout, timing closure, and power analysis. The workshop also enhanced career readiness by exposing students to professional design environments and fostering industry-academia collaboration for internships and joint projects.


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